AMD Zen 6 Chiplet Design Could Enable 24-Core Ryzen CPUs and 144 MB Cache for Gaming X3D Chips

AMD Zen 6 Ryzen X3D 12-core chiplet cache: AMD Zen 6 chiplet design: AMD has revealed that its upcoming Zen 6 architecture packs 12 cores and 48 MB of shared L3 cache per chiplet, a potential path to 24-core Ryzen CPUs and larger-cache Ryzen X3D gaming processors. Consumer details remain unconfirmed.

AMD Zen 6 Chiplet Design, Digi Mart USA News: AMD’s upcoming Zen 6 architecture could give future Ryzen processors a significant boost in core count and cache capacity. According to a Notebookcheck report, the design supports up to 12 cores per chiplet, which could pave the way for 24-core desktop Ryzen CPUs and new Ryzen X3D gaming processors with more cores and larger caches.

AMD revealed these details during a technical presentation on its upcoming Epyc Venice server processors. The company has not yet announced consumer Ryzen chips based on Zen 6, but both product families share the same underlying CPU design.

Zen 6 packs 12 full-performance cores and 48 MB of shared L3 cache into a core complex die, or CCD. That is a 50% increase in both core count and cache compared with Zen 5, which has eight cores and 32 MB of L3 cache per chiplet.

Cache per core remains unchanged at 4 MB.

The report says this could benefit gaming. Current 12-core Ryzen processors use two chiplets, and communication between separate CCDs adds latency, especially in games that spread workloads across both.

A single 12-core chiplet would allow all cores to share the same L3 cache, and could also simplify future Ryzen X3D processors, which currently need extra scheduling logic to direct games toward cores with access to the 3D V-Cache.

AMD has already demonstrated a similar configuration with its Epyc Venice-X server processors, which combine 48 MB of built-in L3 cache with 96 MB of stacked 3D V-Cache for 144 MB per 12-core chiplet. By comparison, current X3D processors offer 96 MB of total L3 cache per CCD.

Beyond cores and cache, AMD says Zen 6 features better branch prediction, faster recovery from incorrect predictions, an operation cache of roughly 6,750 entries, and a front end capable of delivering up to 18 operations per cycle. These changes are intended to improve instructions per clock (IPC), which could help gaming performance even in titles that do not fully use 12 cores.

AMD’s presentation showed approximately 27% higher geometric-mean IPC for the denser Zen 6c variant across AI and server workloads. This figure does not measure gaming performance or the standard Zen 6 cores, so it should not be treated as a direct indicator of future Ryzen gains.

Much remains unknown about consumer Zen 6 processors, including clock speeds, power consumption and final configurations. The architecture nonetheless gives AMD a chance to combine the gaming advantages of its eight-core X3D processors with the additional cores and cache of its Ryzen 9 lineup.

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